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Your Imagination, Our Creation
GL640USB GL640USB-A
IEEE-1284 to USB Bridge
SPECIFICATION 1.1 June 7, 1999
Genesys Logic, Inc. 10F, No.11, Ln.3, Tsao Ti Wei, Shenkeng, Taipei, Taiwan Tel: +886-2-2664-6655 Fax: +886-2-2664-5757 http://www.genesyslogic.com
GL640USB, GL640USB-A
Index
1. 2. 3. 4. 5. 6. 7. Features.................................................................................................................. 2 Description .............................................................................................................. 3 IEEE 1284 Interface................................................................................................ 3 Pin Configuration .................................................................................................... 4 Pin Descriptions ...................................................................................................... 5 Block Diagram......................................................................................................... 7 8-BIT RISC MCU INSTRUCTION ........................................................................... 9 7.1 MEMORY ORGANIZATION .............................................................................. 9 7.2 MCU FUNCTION REGISTERS ....................................................................... 11 7.3 I/O Register Summary ..................................................................................... 15 7.4 USB Register Summary................................................................................... 22
8. INSTRUCTION SET SUMMARY .......................................................................... 27 9. Advantages of GL640USB .................................................................................... 30 10. EPP Timing ........................................................................................................... 31 10.1 EPP Burst Data Write .................................................................................... 31 10.2 EPP Burst Data Read .................................................................................... 32 11. Electrical Characteristics ....................................................................................... 33 11.1 Absolute Maximum Ratings (Voltages referenced to GND)........................... 33 11.2 DC Characteristics (Digital Pins).................................................................... 33 11.3 DC Characteristics (VCP/D+/D-).................................................................... 34 11.4 Switching Characteristics............................................................................... 35 12. Package ............................................................................................................... 36
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GL640USB, GL640USB-A
1. Features
O O O O O O Low-cost solution for full-speed USB device Applications - Printer, Scanner, PC Camera, External Storage Device, CD-ROM IEEE 1284 interface supports bi-directional communication On-chip EPP engine On-chip 8-bit micro-controller USB Specification Compliance - - O - - - O O O O O O O O O O O O Conforms to USB 12Mbps Specification, Version 1.0 Supports 1 device address and 4 endpoints
2 sets of 64-byte FIFO with dynamic allocation a. 64-In/64-Out b. 64-In0/64-In1 ping pong buffer c. 64-Out0/64-Out1 ping pong buffer
Integrated USB transceiver On-chip 3.3v regulator Improved output drivers with slew-rate control to reduce EMI 12MHz external clock On-chip PLL to support 48MHz internal clock Internal power-on reset(POR) Supports suspend/normal mode power management Customized firmware/driver for scanner application The driver allows current Win98/Win95 OSR-2 printer drivers to print seamlessly to USB Fully plug & play compatible Single-chip solution in cost saving 40-pin SOJ(GL640USB) / 48-pin LQFP(GL640USB-A) Special pad-design to support EPP/USB dual-interface application
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GL640USB, GL640USB-A
2. Description
The GL640USB is a low-cost, single-chip embedded controller designed for connecting an IEEE 1284 parallel port peripheral to USB. It is suitable for applications where the IC is mounted on a PCB inside a product or stand-alone applications where the chip resides in a cable connecting a standard parallel port device to an USB-capable computer. The GL640USB firmware/driver will allow peripheral vendors to easily migrate parallel port device to USB.
3. IEEE 1284 Interface
GPI1-4
GPIO1-7 INIT#
VCP
3.3V output
EPP DEVICE ASIC
WR# WAIT#
ASTRB# DSTRB#
AD[7:0] INT# CLKOUT HRST
GL640USB
D+ D-
USB Port
OSCSEL
CLK12/48
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4. Pin Configuration
40-SOJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLKOUT HRST WR# WAIT# D0 D1 D2 D3 DVCC DGND D4 D5 D6 D7 VCP D+ DAVCC AGND GPI1 ASTRB# DSTRB# INIT# GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 DGND DVCC GPIO2 GPIO1 INT# TEST# GPI4 OSCSEL X1 X2 GPI3 GPI2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
48-LQFP
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 GPIO6 GPIO5 GPIO4 GPIO3 DGND DVCC GPIO2 GPIO1 INT # TEST# GPI4 OSCSEL
Revision 1.1
1 2 3 4 5 6 7 8 9 10 11 12
D0 D1 D2 D3 DVCC DGND D4 D5 D6 D7 VCP D+
GPIO7 INIT# NC DSTRB# ASTRB# NC CLKOUT NC HRST NC WR# WAIT#
X1 NC X2 GPI3 GPI2 NC NC GPI1 AGND NC AVCC D-
24 23 22 21 20 19 18 17 16 15 14 13
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5. Pin Descriptions
GL640USB GL640USB-A SYMBOL I/O Pin No. 1 Pin No. 43 CLKOUT
DESCRIPTION
O Clock output to external device The clock frequency is selected by setting DEVCTL register.
2
45
HRST
I High active hardware reset, internal pull low With internal power-on reset circuit, this pin can be left unconnected or pulled low.
3 4
47 48
WR# WAIT#
O This active low signal indicates the EPP write operation. I this signal acts as the acknowledge from external EPP device, internal pull up
5-8 9 10 11-14 15
1-4 5 6 7-10 11
D0-D3 DVCC DGND D4-D7 VCP
I/O Address/Data bus bit 0 to bit 3 - Digital 5V input - Digital ground I/O Address/Data bus bit 4 to bit 7 - 3.3 V output. This output voltage is used to pull up D+ line to indicate the full-speed device.
16 17 18 19 20 21 22 23 24 25
12 13 14 16 17 20 21 22 24 25
D+ DAVCC AGND GPI1 GPI2 GPI3 X2 X1 OSCSEL
I/O USB differential data I/O USB differential data - Analog 5V input - Analog ground I General purpose input 1 I General purpose input 2 I General purpose input 3 I/O Crystal output I 12/48 MHz crystal or external clock input I Oscillator Select, internal pull down 0=12MHz 1=48MHz
26
26
GPI4
I General purpose input 4, internal pull up
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GL640USB, GL640USB-A
27 27 TEST# I Mode select, internal pull up 1=Normal Mode 28 28 INT# 0=Chip Test Mode
I this is an input pin to accept the interrupt signal from external EPP controller, internal pull up
29 30 31 32 33 34 35 36 37 38 39 40
29 30 31 32 33 34 35 36 37 38 40 41
GPIO1 GPIO2 DVCC DGND GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 INIT# DSTRB# ASTRB#
I/O this signal is served as an general purpose I/O pin, internal pull up I/O this signal is served as an general purpose I/O pin, internal pull up - Digital 5V input - Digital ground I/O this signal is served as an general purpose I/O pin, internal pull up I/O this signal is served as an general purpose I/O pin, internal pull down I/O this signal is served as an general purpose I/O pin I/O this signal is served as an general purpose I/O pin I/O this signal is served as an general purpose I/O pin O output signal to initialize the EPP device. O EPP data strobe O EPP address strobe
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6. Block Diagram
GL640USB
Micro Controller
I/O
Register
USB Control Register
ENDP0
FIFO
USB SIE
FIFO0 (64 bytes) EPP Engine FIFO1 (64 bytes)
This USB controller contains 3 sets of FIFO. The ENDP0 FIFO is an 8-byte FIFO to store/transmit the endp0 control packet. The FIFO0 and FIFO1 are a set of 64-byte ping-pong FIFO for endp1 and endp2. FIFO0 is used for DATA0 packet and FIFO1 is for DATA1 packet. When they are served as the endp1 FIFO, the LINKFF bit of FFCFG should be set and LINKDIR bit of FFCFG should be cleared. It they are allocated as the endp1 FIFO, then LINKDIR should be set.
An EPP engine is included to automatically accessing data to/from external device ASIC. Firmware can set the data length and hardware will count down to decide the last byte.
There are two sets of registers : I/O register and USB register. The USB register is controlled by micro-controller to implement the USB endpoint 0 functions. The I/O register is the main register to interface the data accessing between this controller and external device.
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The internal micro-controller is a proprietary RISC-like, Harvard-architecture 8-bit micro-controller.
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7. 8-BIT RISC MCU INSTRUCTION
7.1 MEMORY ORGANIZATION
The memory in the microcontroller is organized into user program memory in program ROM and data memory in SRAM space.
Program Memory Organization
The 11-bit Program Counter (PC) is capable of addressing 2.25K x 14 of program space. However, the program space of the GL640USB is 2K x 14. The program memory space is divided into two functional groups: Interrupt Vectors and program code. After a reset, the Program Counter points to location zero of the program space. After a timer interrupt, the Program Counter points the location 0x0004 of the program space.
After Reset
Addres s 0x0000 Reset Vector
After Timer Interrupt
0x0004 0x0005
Timer Interrupt Vector
2K x 14 ROM 0x07FF
Figure 7-1 Program Memory Space
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Data Memory Organization
The data memory is partitioned into two Banks which contain the General Purpose Registers, MCU Function Registers and USB Function Registers. Bit RP0 is the bank select bit. RP0 (STATUS<5>) = 1 Bank 1 RP0 (STATUS<5>) = 0 Bank 0 The lower locations of each Bank are reserved for MCU Function Registers. Above the MCU Function Registers are the USB Registers, I/O Registers and General Purpose Registers implemented as SRAM. Both Bank 0 and Bank 1 contain MCU Function Registers. USB Registers are located in Bank 0, and I/O Resgiters are located in Bank 1. Some "high use" MCU Function Registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access. Data Data Memory Memory Address Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 10~1Fh 20h General PCHBUF INTEN USB Registers PORT1 PORT2 INDR TIMER PCL STATUS INDAR 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 90h~9Fh PCHBUF INTEN I/O Registers PORT1CO N PORT2CO N INDR PSCON PCL STATUS INDAR
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GL640USB, GL640USB-A Purpose Registers (64 bytes) 5Fh
Figure 7-2 Data Memory Space
7.2 MCU FUNCTION REGISTERS
Address
Name INDR TIMER PCL STATUS INDAR PORT1 PORT2 PCHBUF INDR PSCON PCL STATUS INDAR PORT1CON PORT2CON PCHBUF
Function Addressing this location will use the content of INDAR to address data memory (not a physical address) Timer register Program Counter's low byte Status register Indirect address register Port 1 data register Port 2 data register Write buffer of Program Counter's bit 10-8 Addressing this location will use the content of INDAR to address data memory (not a physical address) Prescaler control register Program Counter's low byte Status register Indirect address register Port 1 direction control register Port 2 direction control register Write buffer of Program Counter's bit 10-8
Table 7-1 MCU Function Register Summary
00h 01h 02h 03h 04h 06h 07h 0Ah 80h 81h 82h 83h 84h 86h 87h 8Ah
INDR (Address 00h/80h) INDR is not a physical register. Addressing INDR register will cause indirect addressing. Any
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GL640USB, GL640USB-A instruction using the INDF register actually accesses the register pointed by the INDAR register. TIMER (Address 01h, Timer register) R/W TIMER7 R/W TIMER6 R/W TIMER5 R/W TIMER4 R/W TIMER3 R/W TIMER2 R/W TIMER1 R/W TIMER0
After timer is enable, the timer will start to count up. The Timer Interrupt is generated when the TIMER register overflows from FFh to 00h. Value on POR: "0 0 0 0 0 0 0 0" PCL (Address 02h/82h, Program Counter's low byte) R/W PCL7 R/W PCL6 R/W PCL5 R/W PCL4 R/W PCL3 R/W PCL2 R/W PCL1 R/W PCL0
The Program Counter (PC) is 11-bit wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte is not directly readable or writable and comes from PCHBUF. The GL600USB has a 4 level deep x 11-bit wide hardware stake. The stake space is not part of either program or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is poped in the event of a RETIA, RETI or a RET instruction execution. PCHBUF is not affected by a push or pop operation. Value on POR: "0 0 0 0 0 0 0 0" Status (Address 03h, Status register) R/W BS R/W ZO R/W HC R/W CA
BS: Bank Select 1: Bank 1 (80h-FFh) 0: Bank 0 (00h-7Fh) ZO: Zero bit 1: The result of an arithmetic or logic operation is zero 0: The result of an arithmetic or logic operation is not zero HC: Half Carry/Borrow bit 1: A carry-out from the 4th low order bit
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GL640USB, GL640USB-A 0: No carry-out from the 4th low order bit CA: Carry/Borrow bit 1: A carry-out from the most significant bit 0: No carry-out from the most significant bit Value on POR: "- - 0 - - 0 0 0" INDAR: (Address 04h/84h, Indirect address register) R/W R/W R/W R/W R/W R/W R/W R/W INDAR7 INDAR6 INDAR5 INDAR4 INDAR3 INDAR2 INDAR1 INDAR0 Any instruction using the INDF register actually accesses the register pointed by the INDAR register. Value on POR: "x x x x x x x x" [1] Note 1: "x" means unknown PORT1 (Address 06h, Port 1 data register) R/W PORT1. 4 R/W PORT1. 3 R/W PORT1. 2 R/W PORT1. 1 R/W PORT1. 0
PORT1 is a 5-bit latch for Port 1. Reading the PORT1 register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Value on POR: "- - - x x x x x" PORT2 (Address 07h, Port 2 data register) R/W PORT2. 7 R/W PORT2. 6 R/W PORT2. 5 R/W PORT2. 4 R/W PORT2. 3 R/W PORT2. 2 R/W PORT2. 1 R/W PORT2. 0
PORT2 is an 8-bit latch for Port 2. Reading the PORT2 register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Value on POR: "x x x x x x x x" PCHBUF (Address 0Ah/8Ah, Write buffer of Program Counter's bit 10-8) R/W R/W R/W
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GL640USB, GL640USB-A PCHBU F2 PCHBU F1 PCHBU F0
Write buffer for upper 3-bit of Program Counter. The upper byte of Program Counter is not directly accessible. PCHBUF is a holding register for the PC[10:8] whose contents are transferred to the upper byte of the Program Counter. Value on POR: "- - - - - 0 0 0" INTEN (Address 0Bh/8Bh, Interrupt enable register) R/W GIE R/W TMROE N R/W TMROF
GIE: Global interrupt enable bit 1: Enable all interrupts 0: Disable all interrupts TMROEN: Timer overflow interrupt enable bit 1: Enable timer interrupt 0: Disable timer interrupt TMROF: Timer overflow interrupt flag bit 1: Timer register has overflowed 0: Timer register did not overflow Value on POR: "0 - 0 - - 0 - -" PSCON (Address 81h, Prescaler control register) R/W PSDIS PSEN: Prescaler disable bit 1: Disable prescaler for timer 0: Enable prescaler for timer PS[2:0]: Prescaler rate select bits Bit Value 000 001 Timer Rate 1:2 1:4 R/W PS2 R/W PS1 R/W PS0
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GL640USB, GL640USB-A 010 1:8 011 1:16 100 1:32 101 1:64 110 1:128 111 1:256 Value on POR: "- - - - 1 1 1 1" PORT2CON (Address 86h, Port 1 direction control register) R/W R/W R/W R/W P1CON3 P1CON2 P1CON1 P1CON0 All Port 1 pins have data direction control bits which can configure these pins as output or input. Setting a PORT1CON register bit put the corresponding output driver in a hi-impedance mode. Clearing a bit in the PORT1CON register puts the contents of the output latch on the selected pin. Value on POR: "- - - - 1 1 1 1" PORT2CON (Address 87h, Port 2 direction control register) R/W R/W R/W R/W R/W R/W R/W R/W P2CON7 P2CON6 P2CON5 P2CON4 P2CON3 P2CON2 P2CON1 P2CON0 All Port 2 pins have data direction control bits which can configure these pins as output or input. Setting a PORT2CON register bit put the corresponding output driver in a hi-impedance mode. Clearing a bit in the PORT2CON register puts the contents of the output latch on the selected pin. Value on POR: "1 1 1 1 1 1 1 1"
7.3 I/O Register Summary
Mnemonic IODEVCTL ENDPCTL GPI
Revision 1.1
Address (Hex) 90 91 92
Description device control for I/O endpoint control GPI3-1 register
-15Jun. 7, 1999
GL640USB, GL640USB-A INTFLG UINTEN USBFLG CTLDAT/ STSDAT CTLLEN/ STSLEN FFCFG FFCTL FF0DAT FF1DAT LINE_L LINE_H EPPCTL EPPAD
IODEVCTL (offset 90h) R/W EXTCLK EN CLKTYP select crystal frequency, this bit reflects the OSCSEL pin 0 - 12MHz, 1 - 48MHz CKSEL[2:0] select CLKOUT frequency, default=8MHz 000 - stop CLKOUT 001 - 24MHz 010 - 16MHz 011 - 12MHz GPI4 this bit reflects the status of GPI4 input pad Enable EXTCLK output 0 - set EXTCLK to tri-state ENDPCTL (offset 91h) 1- enable EXTCLK 100 - 8MHz 101 - 6MHz 110 - 12KHz R/O NC R/O NC R/O GPI4 R/W CKSEL2 R/W CKSEL1 R/W CKSEL0 R/O CLKTYP
93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
interrupt flag USB interrupt enable USB interrupt flag Control/status data buffer Control/status data length FIFO configuration register FIFO control data port for FIFO0 data port for FIFO1 Read : max. length of TX data packet Write : line size (low byte) Read : received data length / Write : line size (high byte) EPP control / status EPP interface AD0-7
EXTCLKEN -
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GL640USB, GL640USB-A
R/W EP3STL Default=8'h00 EPnSTL Endpoint n is stalled By setting EPnSTL to `1', endpoint n will respond with a STALL to incoming USB packet. R/W EP2STL R/W EP1STL R/W EP0STL
GPI (offset 92h) R/O GPI3 R/O GPI2 R/O GPI1
INTFLG ( offset 93h ) R/O
Reserved
R/W1C
RESUME
R/W1C
SUSPND
R/W1C
EPPINT
R/O
Reserved
R/O
EP3TX
R/W1C
DATARX
R/W1C
DATATX
Default=8'h00 This register is used to identify the exact interrupt event. When the external controller receives an interrupt, it should first read this register to check the interrupt event. Writing `1' to clear the individual interrupt bit.
DATATX DATARX EP3TX EPPINT -
The endp1 transmits a data packet completely The endp2 receives a data packet Endp3 transaction is detected
- This bit means external EPP interrupt is detected. The EPPTXEN/EPPRXEN is cleared by hardware when this bit is set.
SUSPND RESUME UINTEN ( offset 94h ) R/W FFINT R/W REMINT
USB suspend request is detected. USB resume request is detected.
R/W SUSINT
R/W DMAINT
R/O Reserved
R/W UINTEN
R/W DRXINT
R/W DTXINT
These are the interrupt enable bits of INTFLG register. Default = 8'h00 USBFLG ( offset 95h ) R/W1C R/O R/O
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GL640USB, GL640USB-A
STSTX Default=8'h00 STSTX The interrupt endpoint 3 transmits a status packet completely Reserved Reserved
CTLDAT/STSDAT ( offset 96h ) R/W
CTLDAT7
R/W
CTLDAT6
R/W
CTLDAT5
R/W
CTLDAT4
R/W
CTLDAT3
R/W
CTLDAT2
R/W
CTLDAT1
R/W
CTLDAT0
Read: Write:
Pop data from endp0/endp3 FIFO. Push data into endp0/endp3 FIFO.
CTLLEN/STSLEN ( offset 97h ) R/O
RXSETUP
R/O
RXOUT
R/W
DATOG
R/W
CTLLEN3
R/W
CTLLEN2
R/W
CTLLEN1
R/W
CTLLEN0
For the received OUT/SETUP transaction on endp0/endp3, read this register to check the data size and data toggle, and then read the received data from CTLDAT/STSDAT register. To transmit data on endp0/endp3, first push data into endp0/endp3 FIFO, and then write this register to set data size and data toggle. Finally, turn on CTLTXEN or STSTXEN bit to enable the data transmission. CTLLEN3-0 DATOG RXOUT RXSETUP Length of the received/transmitted endp0/endp3 data Data toggle of the received/transmitted endp0/endp3 data The received transaction is an OUT transaction
The received transaction is a SETUP transaction
FFCFG ( offset 98h ) R/W
TX64ONLY
R/W
TXNULL
R/W
DMARXEN/ EPPRXEN
R/W
DMATXEN/E PPTXEN
R/W
LINKDIR
R/W
LINKFF
Default=8'h00
This register is used to control TX/RX FIFO and DMA/EPP engine operation.
LINKFF LINKDIR
-
link RXFIFO to TXFIFO together to form ping-pong FIFO This bit is valid only when LINKFF is set to 1. 1: the ping-pong FIFO is used for end2
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0: DMATXEN DMARXEN the ping-pong FIFO is used for end1
enable DMA/EPP engine to access data into TXFIFO enable DMA/EPP engine to move data from RXFIFO into external Device
TXNULL
-
Set this bit to transmit a zero-byte data on endp1 This bit will be cleared by hardware automatically.
TX64ONLY
-
Transmit 64-byte packet only When this bit is set, data left in FIFO will not be sent if it is not 64 bytes.
Note: When LINKFF is set and LINKDIR is gonna to change, LINKFF should be cleared to `0' first and then change LINKDIR and set LINKFF again.
FFCTL ( offset 99h ) W/O
FF0RST
W/O
RXFFRST
W/O
TXFFRST
R/W
STSTXEN
R/W
DRXDIS/ DTX1EN
R/W
DTX0EN
R/W
CTLRXDIS
R/W
CTLTXEN
CTLTXEN -
enable endpoint 0 transmitting This bit is cleared by hardware when CTLTX interrupt is set.
CTLRXDIS DTXEN
-
disable endpoint 0 receiving turn on this bit to enable endpoint 1 data packet transmission. If LINKFF=1, it indicates the TXFIFO0 is ready. This bit is cleared by hardware when DATATX interrupt is set.
DRXDIS
-
disable RXFIFO receiving If this bit is set, NAK will be responded to the OUT token. Data in RXFIFO is kept unchanged. If LINKFF=1, this bit means the TXFIFO1 is ready.
STSTXEN -
enable endpoint 3 transmitting This bit is cleared by hardware when STSTX interrupt is set.
TXFFRST RXFFRST FF0RST
-
reset TXFIFO, cleared by hardware itself.
reset RXFIFO, cleared by hardware itself reset CTL/STS FIFO, cleared by hardware itself
FF0DAT ( offset 9Ah )
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R/W FFDAT7 R/W FFDAT6 R/W FFDAT5 R/W FFDAT4 R/W FFDAT3 R/W FFDAT2 R/W FFDAT1 R/W FFDAT0
Read this register will pop data from FIFO0. Write this register will push data into FIFO0.
FF1DAT ( offset 9Bh ) R/W FFDAT7 R/W FFDAT6 R/W FFDAT5 R/W FFDAT4 R/W FFDAT3 R/W FFDAT2 R/W FFDAT1 R/W FFDAT0
Read this register will pop data from FIFO1. Write this register will push data into FIFO1.
MAXLEN/LINE_L ( offset 9Ch ) R/W LINE7 Read: MAXLEN Write: LINE_L The low byte of EPP accessing length Equal to 64 R/W LINE6 R/W LINE5 R/W LINE4 R/W LINE3 R/W LINE2 R/W LINE1 R/W LINE0
DATLEN / LINE_H ( offset 9Dh ) R/W LINE15 Read: DATLEN Write: LINE_H The high byte of EPP accessing length The length of data received by the RX endpoint R/W LINE14 R/W LINE13 R/W LINE12 R/W LINE11 R/W LINE10 R/W LINE9 R/W LINE8
EPPCTL ( offset 9Eh ) R/W
GLTHFLT
R/W
WRCHK
R/W
ACTIVE
R/W
A2CHK
R/W
A1CHK
R/W
A0CHK
R/O
INT_
R/W
ADOE
This register is available only in EPP mode. ADOE Set this bit to `1' can drive data in EPPAD register to pins D7-0 INT_ This bit reflects the status of INT_ pin.
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GL640USB, GL640USB-A
AnCHK This bit is used to select the type of EPP read engine 1 - EPP engine will check An pin before starting an EPP cycle. 0 - EPP engine doesn't check An pin , n=0~2 ACTIVE Select the An pin polarity 1 - active high for data ready 0 - active low for data ready WRCHK Select EPP check status during write or read 1- Check during EPP write cycle 0 - check during EPP read cycle GLTHFLT Filter glitches on WAIT_ 1- Enable filter, performance maybe slow down 0 - Disable filter
EPPAD ( offset 9Fh ) R/W
EPPAD7
R/W
EPPAD6
R/W
EPPAD5
R/W
EPPAD4
R/W
EPPAD3
R/W
EPPAD2
R/W
EPPAD1
R/W
EPPAD0
This register is used to set/read pins D7-0. To set D7-0, except writing EPPAD, the ADOE bit of EPPCTL register is set to 1 Read this register can get the status of pins D7-0.
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GL640USB, GL640USB-A
7.4 USB Register Summary
Mnemonic
DEVCTL EVTFLG DEVADR RXCTL0 TXCTL0 CTLDAT MISC GPIO GPIOCTL
Offset
10h 11h 12h 13h 14h 15h 16h 17h 18h
Description
Device control register USB function interrupt flag USB Device address Endpoint 0 RX control Endpoint 0 TX control Endpoint 0/3 FIFO data port Miscellaneous register GPIO value GPIO direction control
Remarks
DEVCTL ( offset 10h ) R/W
DISGLUSB
R/W
EP0STL
R/W
WAKE
R/W
WAKEDIS
R/W
PWRDN
Default=8'h10 PWRDN Power down mode If USB suspend is detected, firmware can set PWRDN to put the controller into power down mode. Power down mode stops oscillator and freezes all clocks at known states, and no more command can be executed. Hardware will automatically clear PWRDN upon hardware reset or interrupt event. WAKEDIS WAKE Disable remote wakeup capability Wake up host Write `1' to this bit will place USB bus to K state. EP0STL Endpoint 0 stall Endpoint 0 will respond with a STALL to a valid transaction. DISGLUSB Disable GL640USB, and bypass all EPP signals
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GL640USB, GL640USB-A
When this bit is set to `1', D+ and D- pin will be driven to low so that no connect will be detected on the host side.
EVTFLG ( offset 11h ) W/O
S_CTLRX
R/W1C
WAKEUP
R/W1C
RESUME
R/W1C
SUSPD
R/W1C
EP0TX
R/W1C
EP0RX
This register is the main USB interrupt flag for endpoint 0 and power management. The firmware detects endpoint 0 transaction via EP0RX and EP0TX. If firmware can't handle the received endpoint 0 control data, then firmware should write `1' to S_CTLRX and EP0RX. By this, the interrupt will redirect to the external DMA interrupt and the CTLRX bit of USBFLG register will be set. For power management, when a USB suspend is detected, the SUSPD bit will be set to `1'. If the USB host put the bus to `K' state during suspend, then the RESUME bit will be set to `1'. If a remote-wake-up event is detected, then the WAKEUP bit will be set to `1'. All those interrupt status bits can be written `1' to clear.
EP0RX EP0TX SUSPD RESUME
-
Endpoint 0 receives a data packet. Endpoint 0 transmits a data packet completely. USB suspend detected USB resume detected
WAKEUP- remote-wake-up event is detected during suspend state The event is DMA mode: WAKEVT bit is set
EPP mode: INT_ pin is asserted low S_CTLRX- Write 1 to set CTLRX bit of USBFLG All the data in endp0/endp3 FIFO are left unchanged.
DEVADR ( offset 12h )
R/W DEVADR6 R/W DEVADR5 R/W DEVADR4 R/W DEVADR3 R/W DEVADR2 R/W DEVADR1 R/W DEVADR0
This register is used to set USB device address. Default=8'h00
Revision 1.1
-23-
Jun. 7, 1999
GL640USB, GL640USB-A
RXCTL0 ( offset 13h ) R/W
RXDIS
R/O
RXSETUP
R/O
RXOUT
R/O
RXSEQ
R/O
RXCNT3
R/O
RXCNT2
R/O
RXCNT1
R/O
RXCNT0
Default=8'h0e This register is used to check the received data byte count, data toggle, and transaction token on endpoint 0. When the EP0RX interrupt is detected, firmware should first check this register to decide the received data is valid or not. At this time, RXDIS bit is set by hardware to prevent the current data in endp0 FIFO overwritten by next incoming data. After extracting data from endp0 FIFO, firmware should clear RXDIS to enable receiving capability on endp0.
RXCNT[3:0] RXSEQ
-
Received data byte count. 1 - The received data is DATA1 0 - The received data is DATA0
RXOUT RXSETUP RXDIS
-
1 - The received token is OUT.
1 - The received token is SETUP. Disable receiving capability on endpoint 0 Upon successfully receiving a data packet on endpoint 0, hardware will automatically set this bit to `1'. At this time, no more SETUP/OUT data on endpoint 0 can be accepted, hardware will respond with NAK.
0 - Endp0 FIFO is available for data receiving. 1 - Endp0 FIFO is not available
Note: Firmware must take care the data toggle check and decide if current RX data is valid. TXCTL0 ( offset 14h ) R/W TXOE Default=8'h00 This register is used to control the data byte count, data toggle of the transmitted data on endpoint 0. If there is data to be sent to endpoint 0, firmware should first push data into FFDAT0 register, and then set the pushed byte count to TXCNT3-0, set the data toggle to TXSEQ, and finally turn on TXOE to enable the data transmission. R/W TXSEQ R/W TXCNT3 R/W TXCNT2 R/W TXCNT1 R/W TXCNT0
Revision 1.1
-24-
Jun. 7, 1999
GL640USB, GL640USB-A
TXCNT3-0 TXSEQ TXOE number of bytes to send 0 - TX DATA0 1 - TX DATA1
ready to transmit control data
CTLDAT ( offset 15h ) R/W FFDAT7 R/W FFDAT6 R/W FFDAT5 R/W FFDAT4 R/W FFDAT3 R/W FFDAT2 R/W FFDAT1 R/W FFDAT0
This register is the window to push/pop data from endp0/3 FIFO. Write to push FIFO, read to pop.
MISC ( offset 16h ) R/O
SUSPD
R/O
ADDR
R/O
DEFLT
R/O
POWER
R/O
Reserved
W/O
FFRST0
R/W
SF
R/W
SUS_DIS
Default = 8'h10 This register is mainly used in testing purpose. SUS_DIS SF Disable suspend detection Short frame mode, used in suspend detection 0=normal mode, needs 3ms bus idle to enter suspend mode 1=short frame mode, needs only 200us to enter suspend mode FFRST0 Reset endpoint 0 FIFO read/write pointer. Data in FIFO remain unchanged. POWER DEFLT ADDR SUSPD Device is in the powered state Device is in the default state Device is in the address state Device is in the suspend state
GPIO ( offset 17h ) R/W GPIO7 R/W GPIO6 R/W GPIO5 R/W GPIO4 R/W GPIO3 R/W GPIO2 R/W GPIO1
GPIOCTL ( offset 18h ) R/W
GPIO7OE
R/W
GPIO6OE
R/W
GPIO5OE
R/W
GPIO4OE
R/W
GPIO3OE
R/W
GPIO2OE
R/W
GPIO1OE
Revision 1.1
-25-
Jun. 7, 1999
GL640USB, GL640USB-A
GPIO and GPIOCTL registers are available only in EPP mode. GPIOCTL register determines pin GPIO1-7 is input mode or output mode, GPIO register is used to set the output data to pin GPIO1-7 or read data from pin GPIO1-7 input.
GPIOnOE -
1= set pin GPIOn to output mode 0= set pin GPIOn to input mode
Revision 1.1
-26-
Jun. 7, 1999
GL640USB, GL640USB-A
8. INSTRUCTION SET SUMMARY
Operand Field Descriptions
Field r A i b
Instruction Set Description
Description Register address Accumulator Immediate data Bit address within a 8-bit register
Mnemonic, Operands Arithmetic Operations ADDAR r, A ADDAR A, r ADDAI i INCR r INCR A, r INCRSZ r INCRSZ A, r SUBAR r, A SUBAR A, r SUBIA i
Cycle s 1 1 1 1 1 1 or 2 1 1 1
Flags Affected CA, HC, ZO CA, HC, ZO CA, HC, ZO ZO ZO
Add r and A, r <- r + A Add A and r, A <- A + r Add A and i, A <- A + i Increment r, r <- r +1 Increment r, A <- r + 1 Increment r, A <- r +1, skip if (A = 0) Subtract A from r, r <- r - A Subtract A from r, A <- r - A Subtract A from i, A <- i - A
Increment r, r <- r +1, skip if (r = 0) 1 or 2
CA, HC, ZO CA, HC, ZO CA, HC,
Revision 1.1
-27-
Jun. 7, 1999
GL640USB, GL640USB-A ZO DECR r DECR A, r DECRSZ r DECRSZ A, r CLRR r CLRA NOP Logical Operations ANDAR r, A ANDAR A, r ANDAI i CMPR r CMPR A, r ORAR r, A ORAR A, r ORIA i XORAR r, A XORAR A, r XORIA i Bit-wise Operations BCR r, b BSR r, b BTRSC r, b BTRSS r, b MOV r, A MOV A, r MOVIA i Shift Operations SWAPR r Swap high and low nibbles in r 1 Bit clear r, r.b <- 0 Bit set r, r.b <- 1 Bit test r, skip if (r.b = 0) Bit test r, skip if (r.b =1) Move A into r, r <- A Move r into A, A <- r Move i into A, A <- i 1 1 1 or 2 1 or 2 1 1 1 ZO And r and A, r <- r & A And A and r, A <- A & r And A and i, A <- A & i Complement r, r <- r ^ FF Complement r, A <- r ^ FF Inclusive OR r with A, r <- r | A Inclusive OR A with r, A <- A | r Inclusive OR i with A, A <- A | i Exclusive OR r with A, r <- r ^ A Exclusive OR A with r, A <- A ^ r Exclusive OR i with A, A <- A ^ i 1 1 1 1 1 1 1 1 1 1 1 ZO ZO ZO ZO ZO ZO ZO ZO ZO ZO ZO Decrement r, r <- r -1 Decrement r, A <- r -1 Decrement r, r <- r-1, skip if (r = 0) 1 1 1 or 2 ZO ZO
Decrement r, A <- r - 1, skip if (A = 1 or 2 0) Clear r, r <- 0 Clear A, A <- 0 No operation 1 1 1 ZO ZO
Data Movement Operations
Revision 1.1
-28-
Jun. 7, 1999
GL640USB, GL640USB-A RLR r RRR r CALL i JUMP i RETIA RETI RET Rotate r left through C Rotate r right through C Call subroutine Jump to address Return and load i to A Return from interrupt Return from subroutine 1 1 2 2 2 2 2 CA CA
Control Transfer Operations
Revision 1.1
-29-
Jun. 7, 1999
GL640USB, GL640USB-A
9. Advantages of GL640USB
Advantage
EMI consideration
Description
1. Operates at 12MHz frequency to reduce EMI radiation 2. Slew rate controlled output pads: All the transition on output pads are well controlled to reduce the EMI radiation.
Cost Saving
1. Provide clock output, no other crystal required. The clock frequency can be 24, 16, 12, 8, 6 MHz 2. Build in power-on reset circuit. No reset circuit required. 3. Provide 3.3V output to pull-up USB bus
Flexibility
1.
Provide self-Isolation capability. With this capability, a device can be designed to support both EPP and USB interface.
2.
Provide additional 7 GPIO pins and 4 GPI pins. These pins can be used as testing purpose, status indication, product selection, ... and so on.
3.
Customized firmware: Contains a RISC controller with 2K ROM, user can developing its own firmware to achieve best performance and satisfy special applications
4.
Support 93C46 to provide external VID and PID
Performance
1. Build in hardware EPP engine and 2 sets of 64 byte ping-pong FIFO, the performance for Bulk transfer will be up to 1.1 Mbytes /sec 2. Balanced architecture: Both the Bulk-In and Bulk-Out can achieve 1.1 Mbytes/sec transfer rate.
Revision 1.1
-30-
Jun. 7, 1999
GL640USB, GL640USB-A
10. EPP Timing
10.1 EPP Burst Data Write
DSTRB#
WR#
WAIT#
PD7-0
NAME
TA TB
Description
Wait# de-assert to DSTRB# de-assert End of EPP write cycle to beginning of next EPP write cycle
Min
42 83
Max
83 83
UNIT
ns ns
TC TD TE
Wait# assert to WR# de-assert WR# assert to data available WR# de-assert to data invalid
42 0 2
83 10
ns ns ns
Revision 1.1
-31-
Jun. 7, 1999
GL640USB, GL640USB-A
10.2 EPP Burst Data Read
DSTRB#
WR# WAIT#
PD7-0
NAME
TA TB TC TD
Description
Wait# de-assert to DSTRB# de-assert Wait# assert to next DSTRB# assert Data available to DSTRB# deasserted DSTRB# de-assert to data invalid
Min
42 83 5 5
Max
83 124
UNIT
ns ns ns ns
Revision 1.1
-32-
Jun. 7, 1999
GL640USB, GL640USB-A
11. Electrical Characteristics
11.1 Absolute Maximum Ratings (Voltages referenced to GND)
SYMBOL
VCC VI VI/O VAI/O VI/OZ VESD DC supply voltage DC input voltage DC input voltage range for I/O DC input voltage for USB D+/D- pins DC voltage applied to outputs in High Z state static discharge voltage
Description
MIN
-0.5V -0.5V -0.5V -0.5 -0.5V 4000V
MAX
+7V VCC+0.5V VCC+0.5V VCC+0.5V VCC+0.5V
11.2 DC Characteristics (Digital Pins)
SYMBOL
PD VDD IO VIL VIH VTLH VTHL VHYS VOL VOH IOLK Power Dissipation Power Supply Voltage DC output sink current excluding D+/D-/VCC/GND LOW level input voltage HIGH level input voltage LOW to HIGH threshold voltage HIGH to LOW threshold voltage Hysteresis voltage LOW level output voltage when IOL=4mA HIGH level output voltage when IOH=4mA Leakage current for pads with internal pull up or pull down resistor RDN RUP Pad internal pulldown resister (Note 1) Pad internal pullup resister (Note 2) 20K 24K 28K 33K 41K 48K Ohms Ohms 2.4 38 2.0 1.7 0.9 0.6 1.8 1.1 0.7 2.0 1.3 0.85 0.4
Description
MIN
9 4.5 4
TYP
10 5.0
MAX
11 5.5
UNIT
mA V mA
0.9
V V V V V V V A
Revision 1.1
-33-
Jun. 7, 1999
GL640USB, GL640USB-A
Note 1 : Pins with internal pullup resister : PIN3, 4, 26, 27, 28, 29, 30, 33, 38, 39, 40 Note 2 : Pins with internal pulldown resister: PIN25, 34
11.3 DC Characteristics (VCP/D+/D-)
SYMBOL
V3.3 I3.3 VOL VOH VDI VCM VSE CIN ILO ZDRV VCP regulator output VCP maximum supply current D+/D- static output LOW(RL of 1.5K to 3.6V ) D+/D- static output HIGH (RL of 15K to GND ) Differential input sensitivity Differential common mode range Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance -10 28 2.8 0.2 0.8 0.2 20 +10 43 2.5
Description
MIN
3.0 27
TYP
3.3 41
MAX
3.6 56 0.3 3.6
UNIT
V mA V V V V V pF A Ohms
Revision 1.1
-34-
Jun. 7, 1999
GL640USB, GL640USB-A
11.4 Switching Characteristics
SYMBOL
FX1 TCYC TX1L TX1H Tr30pf X1 crystal frequency X1 cycle time X1 clock LOW time X1 clock HIGH time Output pad rise time from 10% to 90% swing with 30pF loading Tf30pf Output pad fall time from 10% to 90% swing with 30pF loading Tr50pf Output pad rise time from 10% to 90% swing with50pF loading Tf50pf Output pad fall time from 10% to 90% swing with 50pF loading TrUSB TfUSB D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading 4 4 20 20 ns ns 7.7 10 16 ns 9.5 13 19 ns 5.3 7 10.4 ns 0.45Tcyc 0.45Tcyc 6 8 12
Description
MIN
11.97
TYP
12 83.3
MAX
12.03
UNIT
MHz ns ns ns ns
Revision 1.1
-35-
Jun. 7, 1999
H
10TYP
E
A2
A1
-36A
Revision 1.1
12. Package
40-SOJ
UNIT : MIL
SYMBOLS A A1 A2 D E H 430 130 0.24 106
MIN
NOR 134 110 1025 BSC. 400 BSC. 440
MAX. 138 114
18TYP
50TYP
25TYP
D
GL640USB, GL640USB-A
450
Jun. 7, 1999
GL640USB, GL640USB-A
48-LQFP SYVBOIS A A1 A2 C1 D D1 E E1 e b L L1 MIN 0.05 1.35 0.09 9.00BSC 7.00BSC 9.00BSC 7.00BSC 0.5BSC 0.17 0.45 1 REF MAX 1.6 0.15 1.45 0.16
0.27 0.75
Revision 1.1
-37-
Jun. 7, 1999
GL640USB, GL640USB-A
D D1
E
0.25
E1
L L1
b e
C1
A2
Revision 1.1
A
-38-
Jun. 7, 1999
A1

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